Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2001-04-05
2004-06-22
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S690000, C257S758000, C257S778000
Reexamination Certificate
active
06753612
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The invention relates generally to a high semiconductor chip package, and more particularly, to a structure for flip-chip joinable contact pads on a surface of a chip carrier.
2. Related Art
The related art provides flip-chip assemblies including a substrate having plated-on attach pads for joining semiconductor chips or other substrates. Ball Grid Array (BGA) chip packages are typically constructed with a substrate (e.g., chip carrier) that supports the integrated circuit and which has a substrate core that is constructed with conventional printed circuit board processes, such as lamination. The exterior planar surfaces i.e., top and bottom surfaces) of the substrate each contain a plurality of exposed plated-on metal attach pads (e.g. plated-on copper pads). Typically, a solder ball is placed onto each exposed attach pad. The solder balls are then heated and reflowed to bond the balls to the plated-on metal attach pads. Each of the plated-on attach pads is then physically and electrically connected through the solder ball to a corresponding metallized pad on the chip's surface or on the surface of another substrate.
The related art forms the attach pads on the exterior surfaces of a substrate by employing metal plating techniques (e.g., electroless copper plating followed by Ni/Au plating). The metallization process typically employed to produce the plated-on attach pads of the related art comprises external plating steps and is relatively time consuming and expensive.
SUMMARY OF THE INVENTION
The present invention eliminates the need for surface metallization plating steps in the formation of external contact pads while providing an economical method of forming “flip-chip joinable” contact metallurgy on the surface(s) of a substrate (e.g, a high density chip carrier). As will be further described, the electrical connections between the substrate surface and a flip-chip and the resulting structure are constructed economically using selectively deposited conductive material (e.g., conductive paste, or solder paste).
Accordingly a structural aspect of the invention, provides a substrate having a dielectric layer between a first metal layer and a second metal layer, the second metal layer being disposed above the first metal layer, the first metal layer having a first contact area, the second metal layer having a selected area disposed above the first contact area; and a microvia cavity within the selected area being disposed through the second metal layer and through the dielectric layer and extending to the first contact area of the first metal layer; a mass of conductive material forming a layer upon the selected area of the second metal layer and being inside the microvia cavity and being in contact with the first contact area of the first metal layer.
Another feature of the present invention provides a method for forming contact pads on a substrate, comprising providing a substrate including a first metal surface and an external metal foil layer and a layer of dielectric material disposed between the first metal surface and the external metal foil layer; perforating the external metal foil layer and the dielectric layer to expose a portion of the first metal surface; selectively depositing a conductive material upon the exposed portion of the first metal surface and upon a peripheral area of the external metal foil layer around the exposed portion of the first metal surface; etching the external metal foil layer using the selectively deposited conductive material as an etch mask.
The foregoing and other features of the invention will be apparent from the following more particular description of embodiments of the invention, as illustrated in the accompanying drawings.
REFERENCES:
patent: 5261593 (1993-11-01), Casson et al.
patent: 5372666 (1994-12-01), Kawasaki
patent: 5665650 (1997-09-01), Lauffer et al.
patent: 5706178 (1998-01-01), Barrow
patent: 5875102 (1999-02-01), Barrow
patent: 6010769 (2000-01-01), Sasaoka et al.
patent: 6046505 (2000-04-01), Howard
patent: 6072242 (2000-06-01), Son
patent: 6329610 (2001-12-01), Takubo et al.
patent: 3161956 (1991-07-01), None
patent: 11330295 (1999-11-01), None
patent: WO 99/57762 (1999-11-01), None
Adae-Amoakoh Sylvia
Kresge John S.
Markovich Voya R.
Youngs, Jr. Thurston B.
Andujar Leonardo
Flynn Nathan J.
Schmeiser Olsen & Watts
Steinberg William H.
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