Eclipz wiretest for differential clock/oscillator signals

Details Eclipz wiretest for differential clock/oscillator signals Eclipz wiretest for differential clock/oscillator signals

2007-08-21

2007-08-21

Bui, Bryan (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C327S136000, C327S331000, C327S025000

Reexamination Certificate

active

11055829

ABSTRACT:
A method, apparatus, and computer program product in a data processing system for testing differential clock or oscillator signals. A method is comprised of the following steps: A first single-ended receiver is connected to a positive leg of a differential pair, and a second single-ended receiver is connected to a negative leg of the differential pair. An output of the first single-ended receiver is inverted and delayed before being input into a first RS Flip-Flop. An output of the second single-ended receiver is delayed before being input into a second RS Flip-Flop. An output of a differential receiver is inverted and input into the first and second RS Flip Flops as reset signals. Then a Wire OK signal is output indicating the condition of the legs of the differential pair.

REFERENCES:
patent: 4692932 (1987-09-01), Denhez et al.
patent: 6313709 (2001-11-01), Nishimura et al.

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