ECL/TTL tristate buffer

Details ECL/TTL tristate buffer ECL/TTL tristate buffer

1989-11-15

1991-02-26

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, 307456, 307473, H03K 1902

Patent

active

049964526

ABSTRACT:
An ECL/TTL translation circuit for translating ECL level input signals, which have a high voltage state and a low voltage state, to TTL level output signal, which have a high voltage state and a low voltage state. The translation circuit includes an ECL input circuit, a level shifter, a TTL output circuit a tristate controller. The ECL input circuit receives the ECL level input signals and generates an intermediate voltage signal corresponding to the ECL level input signal. The level shifter is coupled to the ECL input circuit and maintains the intermediate voltage signal in a desired range of voltages. The TTL output circuit receives the intermediate voltage signal and generates a TTL output signal that corresponds to the intermediate voltage signal and, therefore, corresponds to the ECL input signal. The tristate controller receives the tristate signal and causes the TTL output circuit to enter a high impedance mode when a high level tristate signal is received.

REFERENCES:
patent: 4623803 (1986-11-01), Thompson et al.
patent: 4644194 (1987-02-01), Birrittella et al.
patent: 4677320 (1987-06-01), Hannington
patent: 4678944 (1987-07-01), Williams
patent: 4857776 (1989-08-01), Khan

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