ECL to TTL translator circuit with improved slew rate

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307443, 307455, 307456, H03K 19003

Patent

active

051011247

ABSTRACT:
An ECL to TTL translator circuit incorporates an ECL input gate, a TTL output gate, and a voltage amplifier transistor element circuit coupled between the ECL input gate and TTL output gate for effecting the translation. The ECL gate has differential ECL inputs for receiving ECL input signals at least at one of the ECL inputs (V.sub.IN) and differential first and second ECL output nodes (A, B). First and second emitter follower output circuits (Q7, Q3) are coupled to the respective first and second ECL output nodes (A, B). The TTL gate (12) has a TTL output (V.sub.OUT) for delivering TTL output signals corresponding to ECL input signals. The TTL gate phase splitter transistor element (Q9) controls the TTL output (V.sub.OUT). The collector node of a voltage amplifier transistor element (Q6) is coupled to a base node of the phase splitter transistor element (Q9) for controlling the conducting state of the phase splitter transistor element out of phase with the voltage amplifier transistor element. The first emitter follower output circuit (Q7, Q8, R4) is coupled to the base node (C) of voltage amplifier transistor element (Q6) and the second emitter follower output circuit (Q3, Q4, R3) is coupled to the collector node (D) of the voltage amplifier transistor element (Q6) for controlling the conducting state of (Q6) in accordance with ECL input signals and for effecting translation with improved output switching speed.

REFERENCES:
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patent: 4678942 (1987-07-01), Kanai et al.
patent: 4912344 (1990-03-01), Yin
patent: 4988898 (1991-01-01), Jansson
patent: 4992681 (1991-02-01), Urakawa et al.
patent: 4999519 (1991-03-01), Kitsukawa et al.
patent: 5015888 (1991-05-01), Ovens

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