ECL to NMOS converter

Details ECL to NMOS converter ECL to NMOS converter

1987-06-30

1988-08-30

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307264, 307444, 307448, H03K 19094

Patent

active

047679514

ABSTRACT:
A circuit for coupling ECL level logic signals to NMOS circuitry first translates the ECL logic swing from the range of -1.6 v to -0.8 v up to the range of about +0.5 v to +1.3 v. This is done by driving the source of an enhancement device with the ECL input signal. This has the further benificial effect of compensating for temperature changes and process related variables. The level shifted signal is then applied to a gain stage for amplification and delivery to the using circuits. If the ECL input signal is available in complementary form then the complement can be used to drive the source of the gain stage; otherwise it should be connected to V.sub.ref of the ECL circuitry.

REFERENCES:
patent: 4342928 (1982-08-01), Gschwendtner et al.
patent: 4406956 (1983-09-01), Clemen et al.
patent: 4437171 (1984-03-01), Hudson et al.
patent: 4647798 (1987-03-01), Crafts et al.
patent: 4709172 (1987-11-01), Williams
Freeman et al., "Level Shifting Circuit", IBM T.D.B., vol. 18, No. 5, Oct. 1975, p. 1450.
Lewis et al., "Bipolar Logic Level to FET Logic Level Buffer Circuit", IBM T.D.B., vol. 19, No. 8, Jan. 1977, pp. 2953-2954.

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