ECL to FET interface circuit for field effect transistor arrays

Details ECL to FET interface circuit for field effect transistor arrays ECL to FET interface circuit for field effect transistor arrays

1985-10-21

1987-02-24

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307264, 307269, 307530, H03K 19092, H03K 513

Patent

active

046459545

ABSTRACT:
An interface circuit for coupling bipolar ECL logic circuit signals to an FET logic array. The interface receives chip select signals and their complement on a dual rail input line. A small signal amplifier comprising an FET amplifier having an input FET transistor connected through its source and gate to the dual rail input terminals, converts the chip enable signal to a high level clocking signal. An FET dynamic sense amplifier receives a bipolar ECL logic level to be converted to an FET logic level, and receives a reference level from the bipolar transistor logic circuit. Upon clocking of the dynamic sense amplifier by the small signal multiplier, the true and complementary FET logic levels corresponding to the input bipolar logic levels are provided by the dynamic sense amplifier.

REFERENCES:
patent: 4396845 (1983-08-01), Nakano
patent: 4417163 (1983-11-01), Otsuki et al.
patent: 4508983 (1985-04-01), Allgood et al.
patent: 4561702 (1985-12-01), McAdams

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