ECL to CMOS voltage translator with bipolar transistor

Details ECL to CMOS voltage translator with bipolar transistor ECL to CMOS voltage translator with bipolar transistor

1991-09-20

1993-01-26

Mis, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307499, 307264, H03K 190175

Patent

active

051824752

ABSTRACT:
An improved circuit for translating ECL level voltages to CMOS level voltages. The circuit of the invention has a voltage gain stage with a bipolar transistor connected to a PMOS transistor, and a resistive loading stage including NMOS transistors. The bipolar transistor functions to increase the speed of the circuit (particularly at high temperatures) by increasing the driving capability of the voltage gain stage. The speed of the circuit will degrade very little at high temperature and high output load conditions, because the current driving capability of the bipolar transistor employed has low sensitivity to output loading and temperature.

REFERENCES:
patent: 5075581 (1991-12-01), Kamata
patent: 5087841 (1992-02-01), Rogers

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