ECL to CMOS translator

Details ECL to CMOS translator ECL to CMOS translator

1988-02-26

1989-02-21

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, 307355, 307358, H03K 19092, H03K 19086, H03K 19003, H03K 1710

Patent

active

048067997

ABSTRACT:
In integrated circuits which include both ECL and CMOS circuits, there is an ECL to CMOS translator which converts ECL logic levels to CMOS logic levels. To convert from ECL to CMOS levels, the ECL logic high is coupled to the base of an NPN transistor which provides a CMOS logic low. The ECL logic low is prevented from being coupled to the base of the NPN transistor. The CMOS logic high is obtained by an analogous second circuit which is responsive to a complementary ECL signal the output of which is coupled to a P channel transistor. The P channel transistor either provides the CMOS logic high output or is non-conductive.

REFERENCES:
patent: 4563600 (1986-01-01), Kobayashi et al.
patent: 4629913 (1986-12-01), Lechner
patent: 4645951 (1987-02-01), Uragami
patent: 4684831 (1987-08-01), Kruest
patent: 4767951 (1988-08-01), Cornish et al.

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