ECL to CMOS translation and latch logic circuit

Details ECL to CMOS translation and latch logic circuit ECL to CMOS translation and latch logic circuit

1991-02-27

1992-09-15

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, 307451, 307481, H03K 19092, H03K 19096

Patent

active

051480611

ABSTRACT:
A logic circuit that is responsive to applied ECL input logic signals for providing complementary CMOS logic output signals at first and second outputs includes a translation and latch circuit as well as feedback circuitry. The logic circuit includes an input buffer circuit that provides ECL differential logic signals to the translation and latch circuit, the latter of which receives a CMOS clocking pulse. The translation and latch circuit is responsive both to the clocking pulse and the differential ECL logic output signals for producing complementary CMOS control signals at first and second outputs which are latched during the duration of the clocking pulse. A feedback circuit comprising a pair of CMOS inverters each coupled respectively to the first and second outputs of the translation and latch circuit provide feedback control signals which are applied respectively to a pair of CMOS output buffer stages in conjunction with the CMOS control signals to produce the CMOS logic output signals. Between clocking pulses the feedback circuit latches the output signals from the pair of output buffer stages.

REFERENCES:
patent: 4437171 (1984-03-01), Hudson et al.
patent: 4806799 (1989-02-01), Pelley, III et al.
patent: 4992681 (1991-02-01), Urakawa et al.

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