ECL to CMOS logic translator

Details ECL to CMOS logic translator ECL to CMOS logic translator

1990-05-29

1991-08-06

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307455, H03K 14092, H03K 14094

Patent

active

050380575

ABSTRACT:
A voltage translator circuit is responsive to applied ECL input signals for providing corresponding CMOS level logic output signals therefrom. The voltage translator circuit includes a pair of substantially identical translator circuits each having an input coupled to an input of the voltage translator circuit and which are supplied a regulated voltage such that the operation thereof is substantially independent of negative power supply variations and temperature. An output stage is coupled between the output of one of the pair of translator circuits and the output of the voltage translator circuit while the output of the other translator circuit is coupled to the output of the voltage translator circuit in order to provide the CMOS level logic output signals.

REFERENCES:
patent: 4453095 (1984-06-01), Wrathall
patent: 4563601 (1986-01-01), Asano et al.
patent: 4644194 (1987-02-01), Birritella
patent: 4697109 (1987-09-01), Honma et al.
patent: 4794317 (1988-12-01), Van Tran
patent: 4797583 (1989-01-01), Ueno et al.
patent: 4906871 (1990-03-01), Iida

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