ECL to CMOS level conversion circuit

Details ECL to CMOS level conversion circuit ECL to CMOS level conversion circuit

1991-03-11

1992-11-10

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307455, H03K 19092, H03K 19086

Patent

active

051626772

ABSTRACT:
A level conversion circuit has an input buffer circuit which includes bipolar transistors and a complementary type inverter circuit which includes a P-channel first field effect transistor and an N-channel second field effect transistor. An input signal having a small amplitude is inputted to directly a gate terminal of the first field effect transistor and to a gate of the second field effect transistor through a coupling capacitor with no time delay. The complementary type inverter circuit outputs an output signal having a large amplitude. The coupling capacitor is interposed between the gates of the first and second field effect transistors forming the inverter circuit and this arrangement enables the level conversion circuit to operate at a high speed and at a reduced power consumption.

REFERENCES:
patent: 4697109 (1987-09-01), Honma et al.
patent: 4779016 (1988-10-01), Sugiyama et al.
patent: 4798981 (1989-01-01), Tsugaru et al.
patent: 4992681 (1991-02-01), Urakawa et al.

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