ECL to CMOS level conversion circuit

Details ECL to CMOS level conversion circuit ECL to CMOS level conversion circuit

1991-11-06

1994-02-15

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307451, 307455, 3072963, H03K 19092, H03K 301

Patent

active

052870197

ABSTRACT:
A level conversion circuit includes an ECL logic circuit including a current switch circuit having first and second transistors, each of the transistors having an emitter coupled to each other and at least one thereof receiving an input signal of ECL logic level, and an output transistor coupled to a collector of at least one of the first and second transistors; a current control circuit including a current mirror circuit having third and fourth transistors, at least one of the transistors being coupled to an output end of the output transistor, and controlling a current flowing through the output to thereby carry out a level conversion of a signal at the output end; and a switch circuit operative coupled to the current control circuit. The switch circuit responds to a control signal and thus controls a supply of a current or a break thereof from the output transistor to the current control circuit. As a result, it is possible to decrease power dissipation in the present level conversion circuit without spoiling high speed operation thereof in a stand-by state of an apparatus or system to which it is applied.

REFERENCES:
patent: 4713560 (1987-12-01), Herndon
patent: 4883988 (1989-11-01), Ide et al.
patent: 4958094 (1990-09-01), Ishii et al.
patent: 4992681 (1991-02-01), Urakawa et al.
patent: 5138199 (1992-08-01), Hirata et al.

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