ECL to CMOS level conversion circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

3072967, 307455, 307451, H03K 1714, H03K 17094

Patent

active

052143287

ABSTRACT:
A level conversion circuit includes an input buffer receiving an ECL level signal, a current mirror circuit receiving the output of the input buffer and a reference voltage and providing a converted CMOS level output signal, and a reference voltage generating circuit. The reference voltage generating circuit includes either a circuit for simulating at least portions of the input buffer, or it includes a circuit for providing a reference voltage to the current mirror circuit which varies in accordance with the level of the input signal.

REFERENCES:
patent: 4068140 (1978-01-01), Lou
patent: 4275313 (1981-06-01), Boll et al.
patent: 4453095 (1984-06-01), Wrathall
patent: 4563601 (1986-01-01), Asano et al.
patent: 4763021 (1988-08-01), Stickel
patent: 4968905 (1990-11-01), Sanwo et al.
patent: 5075579 (1991-12-01), Ueno

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