ECL output buffer circuit with improved compensation

Details ECL output buffer circuit with improved compensation ECL output buffer circuit with improved compensation

1990-04-16

1991-12-10

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307355, 307356, 307310, 307491, H03K 301

Patent

active

050721364

ABSTRACT:
An ECL output buffer circuit for generating a stable predetermined output voltage over power supply, temperature and process variations and having a high speed of operation with low power consumption includes a differential pair formed of first and second input transistors (Q102, Q103), an emitter follower transistor (Q101), a first current source (112), and a second current source (114). The first current source is coupled to the base of the emitter follower transistor for generating a compensating current. The second current source is coupled to the emitters of the first and second input transistors for generating a gate current.

REFERENCES:
patent: 4745304 (1988-05-01), Wilson
patent: 4748346 (1988-05-01), Emori
patent: 4751406 (1988-06-01), Wilson
patent: 4870301 (1989-09-01), Petty
patent: 4980579 (1990-12-01), McDonald et al.
patent: 5003199 (1991-03-01), Chueng et al.
patent: 5013941 (1991-05-01), Jensson
patent: 5025179 (1991-06-01), Freitas

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