ECL mux latch

Details ECL mux latch ECL mux latch

1988-04-01

1989-09-12

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307466, 307467, 307443, 307480, 307243, H03K 19086, H03K 1716, H03K 1900, H03K 1756

Patent

active

048663069

ABSTRACT:
A method and apparatus for providing an emitter coupled logic 2 to 1 multiplexer latch. The latch has a feedback loop for latching data within the loop and at least two data ports for transmitting data. A single differential amplifier having emitter coupled transistors are coupled to the feedback loop and to the data ports and is responsive to control signals to selectively cause either the feedback loop to latch data or a selected one of the data ports to transmit data. The control signals are derived from a single clock signal, its inversion and a select signal. A nonoverlap region is created by raising the voltage range of either the clock signal or its inversion so that A and B latches can be used.

REFERENCES:
patent: 3925691 (1975-12-01), Gaskill et al.
patent: 4041326 (1977-08-01), Robinson
patent: 4258274 (1981-03-01), Nagashima et al.
patent: 4506171 (1985-03-01), Evans et al.
patent: 4628216 (1986-12-01), Mazumder
patent: 4629911 (1986-12-01), Bebernes et al.
patent: 4695749 (1987-09-01), Lam
patent: 4755693 (1988-07-01), Suzuki et al.
Nosowicz, "Cascode Magnitude Compare Circuit", IBM Tech. Disclosure Bulletin, vol. 24, No. 5, Oct. 1981.

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