ECL MOS Buffer circuits

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307446, H03K 19092, H03K 19086, H03K 19094

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active

044530951

ABSTRACT:
An input buffer to which an ECL logic swing is applied through a voltage level shifter to one input of a differential pair of switching devices, the other input of the differential pair being a voltage level shifted by the same amount from an ECL logic reference voltage. The output across a load device coupling one of the switching devices to a collector voltage source drives the input of a conventional inverter coupling a reduced MOS logic voltage supply to the collector voltage source. An output buffer to which a reduced MOS voltage swing logic input is applied to the input of a conventional inverter coupling a reduced MOS logic voltage supply to a collector voltage source. The output of the inverter is applied to one input of a differential pair of switching devices having the other input thereto held at a reference level defined by a voltage divider. The output of the differential pair across a load device coupling one of the switching devices to the collector voltage source is level shifted through another switching device to the circuit output.

REFERENCES:
patent: 3959666 (1976-05-01), Fett et al.
patent: 3974402 (1976-08-01), Fett et al.
patent: 4366397 (1982-12-01), Kitamura et al.
Froment and Marijon, "ECL to TTL Translator Driver", IBM Tech. Disc. Bull., vol. 21, No. 10, 3/1979, pp. 4074-4075.
Hansen and Lane, "Bipolar Driver for Interfacing Bipolar and FET Circuits", IBM Tech. Disc. Bull., vol. 15, No. 1, 6/1972, pp. 41-42.

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