ECL master slice gates with different power levels

Details ECL master slice gates with different power levels ECL master slice gates with different power levels

1990-11-21

1993-08-17

Larkins, William D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307467, 257205, 257539, 257563, H03K 19086, H01L 27118, H01L 27102

Patent

active

052372154

ABSTRACT:
A master-slice type semiconductor integrated circuit device of the invention has a master substrate and a plurality of basic cells provided on the master substrate. Each of the basic cells includes a plurality of resistors and a plurality of transistors. A plurality of wirings are provided in the master substrate to form a predetermined logic circuit. The wirings in each of the basic cells are changed such that the current to flow in each transistor may be selected in a number of ways without the logical amplitude being changed in the logical circuit.

REFERENCES:
patent: 3558992 (1971-01-01), Heuner et al.
patent: 3909636 (1975-09-01), Masaki et al.
patent: 4255672 (1981-03-01), Ohno et al.
patent: 4388755 (1983-06-01), Enomoto et al.
patent: 4748488 (1988-05-01), Suzuki et al.

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