Ecl logic gate using multi-emitter transistors

Details Ecl logic gate using multi-emitter transistors Ecl logic gate using multi-emitter transistors

1988-01-06

1989-04-18

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307291, 3072992, H03K 19086

Patent

active

048230308

ABSTRACT:
A semiconductor circuit arrangement in ECL technology having logical conjunctions between more than two input variables, includes two series-gating stages having ECL current switches, which are controlled by an input variable, each including a reference circuit and at least one control circuit, at least one threshold voltage diode for separating at least two of the logical junctions from one another, further comprising a multiemitter transistor included in the control circuit of the ECL current switch forming the reference circuit, at least one diode-connected transistor having at least two emitters and one collector resistor which forms a logical conjunction of the signal present at the emitters of the diode-connected transistor.

REFERENCES:
patent: 3519810 (1970-07-01), Priel et al.
patent: 3649844 (1972-03-01), Kroos
patent: 4007384 (1977-02-01), Brooks
patent: 4349753 (1982-09-01), Scavuzzo
patent: 4354266 (1982-10-01), Cooperman et al.
patent: 4394657 (1983-07-01), Isogai et al.
patent: 4506171 (1985-03-01), Evans et al.
patent: 4540900 (1985-09-01), Early et al.
Braeckelman et al, "A Masterslice LSI for Subnanosecond Random Logic", ISSCC, Feb. 16-18, 1977, Philadelphia, PA., pp. 108-109.

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