ECL latch circuit having a noise resistance circuit in only one

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307455, 307291, 307443, 307520, 307556, H03K 1716

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active

051441586

ABSTRACT:
A latch circuit including at least three gate circuits, and a noise resistance circuit. A first gate circuit (3, 4, 11, 16) receives a data signal (DT) and a clock signal (CLK). A second gate circuit (1, 7, 13, 17) is connected to an output of the first gate circuit. A third gate circuit (2, 5, 12 18) receives a first inverted clock signal (CLK) at an input terminal. A second input terminal of the third gate circuit is connected to an output of the second gate circuit and is a first output terminal is connected to an input terminal of the second gate circuit, so that a feedback line is formed between the second and third gate circuits. The noise resistance circuit (8, 9, 20, 21) has at least a signal delay element in the feedback line. The noise resistance circuit may include a filter circuit. The noise resistance circuit may also include an amplifier circuit.

REFERENCES:
patent: 3138743 (1964-06-01), Kilby
patent: 3786282 (1974-01-01), Orndorff
patent: 4398105 (1983-08-01), Keller
198, 1977 IEEE Int. Solid-State Circuits Conference Session XVI: High Speed Logic.

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