ECL input buffer for BiCMOS

Details ECL input buffer for BiCMOS ECL input buffer for BiCMOS

1990-12-07

1992-09-15

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307454, 307455, 307446, H03K 19092, H03K 19086

Patent

active

051480603

ABSTRACT:
An ECL buffer circuit includes an input portion for receiving an input signal at an ECL level, a current switch portion and an output portion. The input portion includes a bipolar transistor (Q1), a level-shift diode (D1) and a constant current source (CS1). The current switch portion includes a first and a second switch circuits and a constant current source (CS2). Each switch circuit includes a resistor (R1, R2) and a bipolar transistor (Q2, Q3). The output portion includes a first and a second output circuits and a constant current source (CS3). Each output circuit includes an emitter follower transistor (Q4, Q5) and a bipolar transistor (Q6, Q7). The first output circuit receives an input signal from the input portion, and the second output circuit receives a reference voltage (V.sub.BB). A by-pass resistor (R3, R4) is connected between the base and the emitter of an emitter follower transistor (Q4, Q5) of each output circuit. When the output signal changes from a second level to a first level, the output signal thereby rapidly changes to a predetermined voltage by the emitter follower transistor (Q4, Q5) at first, then changes to a first level by way of the by-pass operation of the by-pass resistor (R3, R4).

REFERENCES:
patent: 4605864 (1986-08-01), Varadarajan et al.
patent: 4682054 (1987-07-01), McLaughlin
patent: 5030852 (1991-07-01), Higashisaka
patent: 5043603 (1991-08-01), Ohba et al.

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