ECL gate having dummy load for substantially reducing skew

Details ECL gate having dummy load for substantially reducing skew ECL gate having dummy load for substantially reducing skew

1988-08-29

1990-12-25

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307475, 307473, 307356, 307358, H03K 19013, H03K 19003, H03K 19086, H03K 19092

Patent

active

049805797

ABSTRACT:
An active dummy load substantially reduces skews for input signals of a CML or an ECL series gate by generating a selectable capacitance that adjusts the delay time of the output signal in relation to the changing of the input signal to one of two states.

REFERENCES:
patent: 4539493 (1985-09-01), Varadarajan
patent: 4609837 (1986-09-01), Yagyuu et al.
patent: 4748346 (1988-05-01), Emori
patent: 4751406 (1988-06-01), Wilson
patent: 4752703 (1988-06-01), Lin
patent: 4760289 (1988-07-01), Eichelberger et al.

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