ECL gate array with collector resistance compensation for distan

Details ECL gate array with collector resistance compensation for distan ECL gate array with collector resistance compensation for distan

1984-11-30

1989-09-12

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, 307264, 307296R, H03K 1986

Patent

active

048663034

ABSTRACT:
An ECL gate array comprising a plurality of basic cells. Each basic cell has a pair of emitter-coupled transistors, and a load connected between the collectors of the transistors and a power supply line. In accordance with a circuit design information, the resistance value of the load can be selected for increasing a noise margin of the output logic levels without deteriorating the switching speed.

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patent: 4435654 (1984-03-01), Koide
M. Suzuki et al., "A 5K-Gate Bipolar Masterslice LSI with a 500 PS Loaded Gate Display," Oct. 1983, vol. SC-18, No. 5, pp. 585-592, IEEE Journal of Solid-State Circuits, New York.
H. D. Varadarajan, "Programmable Swing Current Switch for Low-Power High-Speed Circuits," Mar. 1977, vol. 19, No. 10, pp. 3736-3737, IBM Technical Disclosure Bulletin, New York.
T. Goodman, "F300 Advanced Gate Array Offering Power/Delay Tradeoffs," Apr. 1980-May 13-15, 1980, vol. 5, No. 22/1, Figures 1, 3; p. 4-right-hand column, line 22, Electro/80 Conference Record, Boston, Ma.
H. Mukai et al., "Master Slice", Sep./Oct. 1978, vol. 26, No. 9/10, pp. 1325-1338, Review of the Electrical Communication Laboratories, Tokyo, Japan.
Hiromichi Kimura, "Semiconductor Integrated Circuit Device," Jan. 1984, vol. 8, No. 8, Patents Abstracts of Japan.
Masahiro Ueda, "Transistor Logic Circuit," Mar. 1981, vol. 5, No. 44, Patents Abstracts of Japan.
Nobuo Kunimi, "Logic Circuit," Jun. 1977, vol. 1, No. 58, Patents Abstracts of Japan.

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