ECL cutoff driver circuit with reduced stanby power dissipation

Details ECL cutoff driver circuit with reduced stanby power dissipation ECL cutoff driver circuit with reduced stanby power dissipation

1989-11-01

1991-05-07

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307544, 323315, H03K 301

Patent

active

050139380

ABSTRACT:
The output enable (OE) cutoff driver gate of a cutoff driver circuit is coupled to receive OE signals of high and low potential and hold an ECL logic gate in the cutoff state in response to one of the high and low OE signals. An OE signal driver circuit provides the OE signals of high and low potential to the OE cutoff driver gate. The OE cutoff driver current sink for sinking current from the OE cutoff driver gate is provided by a current switch circuit for switching sinking current on and off in response to current switch signals of high and low potential in phase with the OE signals. The current switch circuit switches on sinking current when the OE cutoff driver gate is holding the ECL logic gate in the cutoff state. The current switch circuit switches off sinking current for reducing power dissipation when the ECL logic gate is out of the cutoff state. The current switch circuit is provided by a current mirror circuit. A first emitter follower output buffer delivers OE signals from an OE input gate to the OE cutoff driver gate. A second emitter follower output buffer delivers current switch signals from the OE input gate to the current mirror circuit in phase with the OE signals.

REFERENCES:
patent: 4517476 (1985-05-01), Barre
patent: 4617478 (1986-10-01), Varadarajar
patent: 4639661 (1987-01-01), Williams et al.
patent: 4713560 (1987-12-01), Herndon
patent: 4795916 (1989-11-01), Liron
patent: 4877977 (1989-10-01), Kokado
patent: 4942369 (1990-07-01), Nakagawara et al.

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