ECL/CML pseudo-rail circuit, cutoff driver circuit, and latch ci

Details ECL/CML pseudo-rail circuit, cutoff driver circuit, and latch ci ECL/CML pseudo-rail circuit, cutoff driver circuit, and latch ci

1989-07-13

1990-07-31

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307473, 307475, 307494, 3072964, 307552, H03K 19086

Patent

active

049452657

ABSTRACT:
A pseudo-rail circuit is coupled between the differential output gate or buffer of an emitter coupled logic or current mode logic (ECL/CML) circuit and the high potential level power rail. The pseudo-rail circuit provides a pseudo-rail node. A first clamp circuit is coupled to the pseudo-rail node for clamping the pseudo-rail node at a first potential level in response to a first control signal. A second clamp circuit is coupled to the pseudo-rail node for clamping at a second potential level in response to a second control signal. A clamp switching circuit alternately applies the first and second clamp circuits to the pseudo-rail node in response to the control signals. As a cutoff driver circuit, the first clamp circuit of the pseudo-rail circuit applies the high potential level of the power rail to the pseudo-rail node. The second claim circuit pulls down the pseudo-rail node to hold the output of the differential output gate in the cutoff state. An output enable (OE) differential gate or buffer provides the clamp switching circuit. The pseudo-rail circuit is incorporated directly in a latch circuit to initiate the cutoff state in response to an OE cutoff signal without losing latched data and without requiring an additional output buffer stage.

REFERENCES:
patent: 4647799 (1987-03-01), Hsu et al.
patent: 4678935 (1987-07-01), Nawata et al.
patent: 4698527 (1987-10-01), Matsumoto
patent: 4806800 (1989-02-01), Khan
patent: 4823028 (1989-04-01), Lloyd
patent: 4838900 (1989-11-01), Umeki
patent: 4857776 (1989-08-01), Khan
patent: 4870301 (1989-09-01), Petty

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