ECL clamped cutoff driver circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307456, 307263, 307270, 307549, 307555, 307557, 307558, 307491, H03K 1986, H03K 512, H03K 301

Patent

active

050251791

ABSTRACT:
An ECL cutoff driver circuit for an ECL gate coupled between ECL high and low potential power rails includes a cutoff clamp circuit. The ECL gate with differential signal inputs and at least one output node is coupled for delivering ECL logic output signals of high and low potential levels during operation of the ECL gate in a switching mode. The cutoff driver circuit includes cutoff transistor elements for shifting down the ECL output at least to a maximum specified cutoff potential level below the ECL logic low potential level in a cutoff state. The cutoff clamp circuit is coupled between the ECL high potential power rail and the output node or output nodes for clamping the ECL output at a minimum or lower bound voltage level substantially at the specified cutoff voltage level V.sub.OLZ. This prevents output buffer transistor elements from being completely turned off for faster return of the ECL gate from the cutoff state to operation in the switching mode. The clamp circuit references the clamp voltage level to the ECL high potential power rail and is substantially independent of the current level in the cutoff clamp circuit.

REFERENCES:
patent: 4877977 (1989-10-01), Kokado

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