ECL circuit with output transistor auxiliary biasing circuit

Details ECL circuit with output transistor auxiliary biasing circuit ECL circuit with output transistor auxiliary biasing circuit

1985-05-03

1988-06-14

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307467, 307296R, H03K 19086, H03K 301

Patent

active

047514060

ABSTRACT:
An ECL circuit comprising an output transistor having a base, a resistor coupled to the base, a first circuit responsive to a deselect signal OE for drawing a first current through the resistor and a second circuit responsive to the deselect signal OE for drawing a second current through the resistor, said first and said second currents combining in said resistor for providing a predetermined turn-off bias potential on said base of said output transistor. The predetermined turn-off bias potential reduces the emitter current of the output transistor such that the noise immunity of a data bus is preserved when a plurality of output transistors are coupled in parallel to the data bus.

REFERENCES:
patent: 3612911 (1978-08-01), Kroos
patent: 4195358 (1980-03-01), Yuen
patent: 4408134 (1983-10-01), Allen

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