ECL Circuit for forcibly setting a high level output

Details ECL Circuit for forcibly setting a high level output ECL Circuit for forcibly setting a high level output

1983-05-27

1985-10-08

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307272R, H03K 19086, H03K 19092, H03K 19003, H03K 1706

Patent

active

045462720

ABSTRACT:
An ECL circuit includes a differential pair of transistors, a set transistor, and a set resistor connected between the emitters of the differential pair of transistors and the emitter of the set transistor. The output of the ECL circuit can be fixed securely to a "high" level only by applying a "high" level signal having the same level as the "high" level signal of the data input to the base of the set transistor.

REFERENCES:
patent: 3321639 (1967-05-01), Fowler et al.
patent: 3396282 (1968-08-01), Sheng et al.
patent: 3780316 (1973-12-01), Wilhelm
patent: 3885169 (1975-05-01), Heightley
patent: 4105942 (1978-08-01), Henry
patent: 4270062 (1981-05-01), Hanna
Patent Abstracts of Japan, vol. 7, No. 84, Apr. 8, 1983.
Review of the Electrical Communication Laboratories, "Master Slice ECL LSI", Mukai et al., vol. 26, No. 9-10, Sep./Oct. 1978, pp. 1325-1337.

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