Echo reduction on bit-serial, multi-drop bus

Details Echo reduction on bit-serial, multi-drop bus Echo reduction on bit-serial, multi-drop bus

1998-12-22

2001-02-20

Lee, Benny (Department: 2817)

Wave transmission lines and networks

Automatically controlled systems

Impedance matching

C333S032000, C333S124000, C326S030000, C710S120000, C710S120000

Reexamination Certificate

active

06191663

ABSTRACT:

TECHNICAL FIELD
The invention relates generally to input/output (I/O) architecture, and more specifically to active echo reduction on a bit-serial, multi-drop I/O bus architecture.
BACKGROUND INFORMATION
Personal computers are in widespread use throughout the world. Most personal computers contain some form of internal block storage device, such as one or more hard drives, CD-ROM drives, CD recorders, tape drives and data cartridge drives, and various other I/O devices which may include some form of programmable memory array. These I/O devices communicate with the internal chipset of the personal computer through a data communication channel, or bus.
With the rapid advancement in processor speed, data communication speed becomes increasingly important. This is especially true where large amounts of information are passed between the personal computer and the I/O device as is common with block storage devices.
High speed, bit-serial I/O is an economical architecture for future personal computers. By using a differential signal on two chip pins, current CMOS (complementary metal-oxide semiconductor) technology can send signals at data rates up to several gigabits per second.
Existing bit-serial I/O standards such as Universal Serial Bus (USB) Specification, Revision 1.1 (dated Sep. 23, 1998), and the Institute of Electrical and Electronics Engineers, Inc. (IEEE) Standard 1394-1995 for a High Performance Serial Bus (approved Dec. 12, 1995 by the IEEE Standards Board and Jul. 22, 1996 by the American National Standards Institute), assume point-to-point wiring. There are two common approaches to such point-to-point wiring.
The first approach is a star bus architecture, with a central hub coupled to and supporting multiple devices. In a star bus architecture, each device communicates only through the hub to the master controller.
FIG. 1
is an example of a star bus architecture I/O system
100
having a chipset
110
coupled to a hub
120
. Hub
120
is coupled to multiple I/O devices
130
, thus allowing communication between the chipset
110
, as a master device, and each I/O device
130
, as a slave device.
The second approach is a daisy-chain bus architecture. In a daisy-chain bus architecture, multiple devices are coupled in series with each device transmitting to, or receiving from, a neighboring device. Communication from one end of a daisy-chain bus architecture to the other commonly involves an approach in which each device relays communications to the next device in the chain. To accomplish this, each device has at least two I/O ports combined with the circuitry to regenerate the incoming signals on the outgoing I/O port.
FIG. 2
is an example of a daisy-chain bus architecture I/O system
200
having a chipset
110
, as a master device, coupled to multiple I/O devices
130
, as slave devices.
Perhaps the most common interface between a personal computer and its block storage devices is the AT Attachment (ATA) interface. The ATA interface has been standardized, in its various renderings, by the American National Standards Institute (ANSI). See, e.g., ANSI X3.298-1997, AT Attachment-
3
Interface (ATA-
3
), approved Sep. 30, 1997. ATA is commonly referred to as IDE (Integrated Device Electronics), referring to the integration of controllers into disk drives, as ATA adopted the IDE technology. The ATA standards define the connectors and cables for physical interconnection between a host system and its internal block storage device, as well as the electrical and logical characteristics of the interconnecting signals. The ATA standards utilize a daisy-chain approach to point-to-point wiring.
Both star bus architecture and daisy-chain bus architecture add cost and complexity to the basic bus architecture through the use of a central hub or multiple I/O ports. An alternative to point-to-point wiring is the use of a multi-drop bus architecture. In a multi-drop bus architecture, a master device can control communications by addressing one or more slave devices across a bus. As such, multi-drop bus architecture commonly use one I/O port for each coupled device.
FIG. 3
is an example of a multi-drop bus architecture I/O system
300
having a chipset
110
, as a master device, coupled to multiple I/O devices
130
, as slave devices.
While the multi-drop bus architecture reduces the cost and complexity associated with point-to-point wiring, multi-drop bus architecture is prone to signal reflections, or echos. This occurs because each cable connection between the bus and a non-receiving device represents a discontinuity for signal energy, thus causing reflections and/or phase-shifted transmissions on the bus. The signal may be reflected back and forth multiple times, causing an oscillatory behavior on the bus, commonly known as “ringing.” Such ringing results in reduced noise immunity, thus leading to reduced signal integrity and reduced operating speeds.
To reduce ringing, the I/O driver circuits for devices attached to a multi-drop bus architecture are often adjusted to match their impedance to the characteristic impedance of the bus. While the impedance of the I/O driver circuit can be adjusted manually, it is common that the I/O driver circuits contain self-adjusting circuitry. Even with impedance matching, multi-drop buses may experience significant reflections.
As will be seen from the above concerns, there exists a need for an improved high-speed bit-serial I/O protocol for coupling I/O devices to a processor, such as an internal chipset of a personal computer. The above mentioned problems with signal reflections and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
SUMMARY
One embodiment of the invention provides a method of active echo reduction on a multi-drop bus having a plurality of I/O devices. The method includes determining whether an I/O device is an intermediate device, determining whether an I/O device is in a non-signaling status, and adjusting an impedance of the I/O device to a high-impedance state when the I/O device is an intermediate device in a non-signaling status.
Another embodiment of the invention provides an I/O device. The I/O device includes an I/O port suitable for coupling to a multi-drop bus and an I/O driver circuit having an impedance and coupled to the I/O port. The I/O driver circuit is adapted to selectively adjust its impedance to a high-impedance state when the I/O device is a non-signaling intermediate device.
A further embodiment of the invention provides a system. The system includes a processor, a multi-drop bus coupled to the processor, and a plurality of I/O devices coupled to the multi-drop bus. Each of the plurality of I/O devices comprises an I/O port coupling the I/O device to the multi-drop bus and an I/O driver circuit having an impedance and coupled to the I/O port. The I/O driver circuit is adapted to selectively adjust its impedance to a high-impedance state when the I/O device is a non-signaling intermediate device.


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“ANSi X3.298-1997, At attachment—3 Interface (ATA-3)”,American National Standards Institute, Copyright by Information Technology Industry Council (ITI), Entire Book (149 pgs, 1998 © Approved Sep. 30, 1997.
“IEEE Standard for A High Performance Serial Bus”,IEEE Std 1394-1995, Copyright by the Institute of Electrical and Electronics Engineers, Inc., Entire Book (372 pgs, (Aug. 30, 1996).
“Universal Serial Bus Specification”, Copyright, Compaq Computer Corporation Revision 1.1, 312 Pages, (Sep. 23, 1998).

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