Echo clock generating circuit of semiconductor memory device...

Details Echo clock generating circuit of semiconductor memory device... Echo clock generating circuit of semiconductor memory device...

2001-05-03

2002-03-05

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S228000, C365S190000, C365S189050

Reexamination Certificate

active

06353575

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to an echo clock generating circuit and manufacturing method therefor appropriate to a synchronous-type semiconductor memory device.
2. Discussion of Related Art
Computers pervade daily life and users demand increasingly higher speed operation as part of higher performance.
In most electronic systems such as a computer etc., a main memory and a cache memory are realized by using random access memory (RAM) chips as the semiconductor memory device, wherein the RAM may be divided into two mutually different categories, namely, a static RAM and a dynamic RAM. Such RAMs types have their own peculiar operational characteristics and applications within the electronic system. For example, static RAM is widely used as the cache memory and dynamic RAM is widely used as main memory.
A synchronous pipeline type semiconductor memory device architecture obtains higher speed operation thereof. In these semiconductor memory devices, devices are provided for transmitting output data, together with echo clocks as indicating signals, to provide data at high speed to a microprocessor or a central processing unit (CPU) etc. For example, the U.S. Pat. Nos. 5,986,948, 5,875,134 or 5,920,511 disclose a technique concerning use of an echo clock to sense a time at which data output by a memory device is valid and stable. The CPU within the electronic system fetches output data at a high speed without error despite an operating environment that may change according to power and temperature etc. It does so by monitoring the echo clock when fetching data output from a semiconductor memory device.
In a typical semiconductor memory device the echo clock is outputted only during a read operation, but in a device such as an SRAM providing double data rate (DDR) operation, the echo clock is outputted during all read and write operations. In such a device, the echo clock is generated by fixing a main data signal line, for use by the echo clock at power voltage or ground voltage, in contrast to sensing a potential level developed on a main data line connected to a sense amplifier and then producing the echo clock. A drawback is that the main data signal line is developed only during a read operation but is not developed during a write operation. So, this conventional method is useful only during a read operation.
Moreover, such a system has the shortcoming that a skew between output data and echo clock edge may become large at times during the operation of the semiconductor memory device.
FIG. 1
shows a circuit block diagram for echo clock generation in a conventional semiconductor memory device. Referring to
FIG. 1
, output data DQ provided through an output buffer
18
and an off-chip driver
20
are first sensed and amplified in a sense amplifier
14
and latched by a data latch
16
through a main data line and a complementary main data line. The data sensed and amplified by the sense amplifier
14
are the read data developed in a memory cell array
10
through a Y path array
12
. When the output data DQ are output through this reading path, an off-chip driver
32
connected to the output of an echo output buffer
30
outputs an echo clock CQ.
As shown in
FIG. 1
, the main data line for an echo clock (an input line of an echo data latch
28
) and the complementary main data line for the echo clock are fixed at a power voltage VDD and a ground voltage GND. During operation of such a system, the skew between the output data DQ and the echo clock CQ is represented as a time difference T shown in FIG.
2
. Those of skill in the art will appreciate that large clock skew is a problem.
FIG. 2
shows an operational timing diagram of clocks of FIG.
1
and related signals.
FIG. 2
illustrates the case where the skew between the output data DQ and the echo clock CQ exceeds nanoseconds, even though the required data output timing is satisfied in accordance with this conventional technique.
Therefore, it is desirable to provide an improved method of minimizing clock skew to prevent a so called “speed push.”
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an echo clock generating circuit and manufacturing method therefor a semiconductor memory device that substantially obviate one or more of the limitations and disadvantages of the related art.
A primary object of the present invention is to provide a semiconductor integrated circuit device capable of substantially solving the above-mentioned problems.
Another object of the present invention is to provide an echo clock generating circuit and manufacturing method therefore appropriate to a synchronous pipeline-type semiconductor memory device architecture.
Yet another object of the invention is to provide an echo clock generating method and therefor circuit, which is capable of minimizing clock skew and preventing so-called ‘speed push’ during an operational cycle.
To achieve these and other advantages, a semiconductor memory device is provided for producing data together with an echo clock as an indicating signal representing the earliest possible time for presenting data in an electronic system. The semiconductor memory device comprises an echo data latch circuit for generating a source signal of the echo clock. It does so in response to an output of a sense amplifier for sensing and amplifying data of a memory cell during a read operation, and for producing the source signal of the echo clock in response to a predetermined level of power voltage during a write operation. The device further comprises an output circuit including an echo clock generating circuit connected between the echo data latch circuit and an echo clock output terminal for receiving the source signal of the echo clock and for outputting the echo clock to the output terminal in response to control data relative to an external clock.
In an another inventive aspect, a method is provided for generating an echo clock in a semiconductor memory device by providing data together with an echo clock as an indicating signal representing the earliest possible time for presenting the data in an electronic system. The method comprises generating an echo clock in response to an output of a sense amplifier for sensing and amplifying the data of a memory cell during a read operation and for producing the echo clock in response to a predetermined level of power voltage during a write operation.
Accordingly, clock skew is minimized or at least greatly reduced yet without a large increase in chip area.


REFERENCES:
patent: 5646571 (1997-07-01), Ohashi
patent: 5875134 (1999-02-01), Cloud
patent: 5920511 (1999-07-01), Lee et al.
patent: 5986948 (1999-11-01), Cloud
patent: 6134180 (2000-10-01), Kim et al.

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