Echo canceller employing dual-H architecture having variable...

Details Echo canceller employing dual-H architecture having variable... Echo canceller employing dual-H architecture having variable...

2007-04-03

2007-04-03

Harold, Jefferey F. (Department: 2646)

Telephonic communications

Echo cancellation or suppression

Using digital signal processing

C379S406090, C379S406080, C379S406050

Reexamination Certificate

active

10602949

ABSTRACT:
An echo canceller circuit for use in an echo canceller system is set forth that provides sensitive double-talk detection. The echo canceller circuit comprises a second digital filter having adaptive tap coefficients to simulate an echo response occurring during the call. The adaptive tap coefficients of the second digital filter are updated over the duration of the call using a Least Mean Squares process having an adaptive gain a. A channel condition detector is used to detect channel conditions during the call. The channel condition detector is responsive to detected channel conditions for changing the adaptive gain a during the call. For example, the channel condition detector may detect the presence of a double-talk condition and set the adaptive gain a to zero. Similarly, the channel condition detector may detect the occurrence of a high background noise condition and set the adaptive gain a to a level less than 1 that is dependent on the detected level of the background noise. Other similar channel conditions and corresponding adaptive gain settings may likewise be utilized.

REFERENCES:
patent: 6031908 (2000-02-01), Laberteaux et al.
patent: 6240180 (2001-05-01), Younce et al.

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