Multiplex communications – Wide area network – Packet switching
Patent
1988-07-22
1990-11-20
Dwyer, James L.
Multiplex communications
Wide area network
Packet switching
379410, H04B 320
Patent
active
049724061
ABSTRACT:
An echo canceller (1) for full duplex digital data transmission in a transmitter/receiver unit when connected via a hybrid circuit (2) to one end of a two wire line (3). In order to provide adequate cancellation at a line data rate of 160 kbit/s over 7-8 km, a data bit history of at least 9 bits is used to address a memory having at least 3 partitions (41-44) with the first partition (41) being addressed by a sequence of at least 3 data bits. This partitioning achieves a small memory size, less than 2 kbits, and a small total chip area for integrated circuit realization of the canceller together with a clocking speed for moderate power consumption is maintained by using serial arithmetic (61-63) for adding the partition outputs together with pipelining (D1, D21-D24). An exponentially quantitizing analog-to-digital converter error signal circuit (9), shown in detail in FIG. 2, is used which has wider application to echo cancellers other than the partitioned memory compensation type.
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Dwyer James L.
The General Electric Company p.l.c.
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