Echo canceler

Details Echo canceler Echo canceler

1992-08-26

1994-10-04

Chin, Stephen

Multiplex communications

Wide area network

Packet switching

379410, 379411, 375 99, H04B 323, H04M 100

Patent

active

053532791

ABSTRACT:
A frame pattern inserter inserts a frame pattern generated by a frame pattern generator periodically into a signal to be transmitted. An echo canceling circuit generates a pseudoecho from the signal to be transmitted with the frame pattern inserted therein and an error signal. A timing controller extracts from a received signal a timing signal to control the frame pattern generator, the frame pattern inserter, and the echo canceling circuit, and outputs a phase signal indicating whether jitter of the timing signal is generated as a leading phase shift or a lagging phase shift. A jitter echo canceling circuit generates a pseudojitter echo from the error signal and the phase signal. The timing controller controls the timing signal to cause the jitter to be generated immediately after the frame pattern is inserted into the signal to be transmitted.

REFERENCES:
patent: 4535206 (1985-08-01), Falconer
patent: 4742510 (1988-05-01), Quatieri, Jr. et al.
patent: 4935919 (1990-06-01), Hiraguchi
patent: 4965823 (1990-10-01), Nakagawa et al.
patent: 4972467 (1990-11-01), Nakagawa et al.
patent: 5018134 (1991-05-01), Kokubo et al.

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