ECC/CRC error detection and correction system

Details ECC/CRC error detection and correction system ECC/CRC error detection and correction system

1988-10-14

1991-06-25

Baker, Stephen M.

Excavating

371 374, G11B 2018

Patent

active

050273574

ABSTRACT:
Occurrence of uncorrectable errors in a stored sector of data which includes a data block, an error checking and correcting (ECC) block and an error detecting (CRC) block is detected. ECC logic is connected to a data bus and responsive to the ECC block in the sector, for generating an error polynomial identifying a location and a value for correctable errors in the sector. CRC logic is connected to the data bus and responsive to the CRC block in the sector for generating a syndrome identifying detected errors in the data block. An evaluation logic circuit is included that is coupled to the ECC logic and the CRC logic and responsive to the error polynomial and the syndrome for generating an uncorrectable error signal if the detected errors do not match the correctable errors. The error checking and correcting code is a Reed-Solomon code as in the X3B11 standard. Likewise the CRC code is a Reed-Solomon code as in the X3B11 standard. The evaluation logic implements a reverse CRC generation polynomial having a plurality of terms in the same order as the error polynomial. Detection logic receives the plurality of terms of the error polynomial, generates an estimated CRC syndrome based on the reverse CRC generation polynomial, and generates the uncorrectable error signal if the estimated CRC syndrome is not equal to the generated CRC syndrome.

REFERENCES:
patent: 4750178 (1988-06-01), Sako et al.
Shao, H. et al., "A VLSI Design of a Pipeline Reed-Solomon Decoder", IEEE Trans. on Computers, May 1985, pp. 393-403.
Adaptec Programmable Storage Controller AIC-010F-10 . . . , preliminary data sheets, Aug. 1986, pp. 1-13, 16-32.
Chien, R., "Cyclic Decoding Procedures for Bose-Chaudhuri-Hocquenghem Codes", IEEE Trans. on Information Theory, Oct. 1964, pp. 357-363.

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