ECC Check bit generation using through checking parity bits

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G06F 1110

Patent

active

043453287

ABSTRACT:
Apparatus for and method of providing single bit error correction and double bit error detection using through checking parity bits. A coding scheme is implemented which uses through checking parity bits appended to each byte as check bits. The remaining check bits are generated such that the combination of through checking parity bits and remaining check bits together provide single bit error correction and double bit error detection.

REFERENCES:
patent: 3755779 (1973-08-01), Price
patent: 4077028 (1978-02-01), Lui et al.
patent: 4077565 (1978-03-01), Nibby, Jr. et al.

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