Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-02-09
2001-07-17
Mills, Gregory (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S705000, C438S725000, C438S715000, C438S714000, C438S686000, C438S671000, C438S240000, C438S393000
Reexamination Certificate
active
06261967
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to a hard mask and etch stop layer structure and a method for forming the hard mask and etch stop layer structure such that that the hard mask is easily removed from underlying layers during semiconductor fabrication processing.
2. Description of the Related Art
Etching of noble metals, such as platinum (Pt) is difficult due to the lack of highly volatile etch by-products at conventional processing temperatures (e.g., <100° C.). Etching of noble materials needs an appropriate etch mask or hard mask which can provide adequate resistance to harsh noble material etching processes.
The use of high wafer temperature processes, such as the temperatures developed during plasma etching, need careful selection of hard mask materials. The mask is to be made of a material that is compatible with the etch process. In addition, the mask material should not lead to stress in the underlying films and must be easy to remove after completion of electrode etch before subsequent depositions.
In dynamic random access memories (DRAM), which employ stacked capacitors, a bottom electrode of the stacked capacitors is often formed from Pt. In the prior art, a single layer oxide mask made up of TEOS oxide has been employed as a hard mask for forming the bottom electrode. Removal of this hard mask after Pt etching is difficult due to the low selectivity of TEOS oxide to other oxides which may be present including layers below the bottom electrode.
Therefore, a need exists for a hard mask layer employed for etching materials, particularly noble materials, which is capable of being easily removed after the etching process.
SUMMARY OF THE INVENTION
A method for forming a patterned shape from a noble metal, in accordance with the present invention, includes forming a noble metal layer over a substrate and patterning a hard mask layer on the noble metal layer. The hard mask layer includes a mask material that is selectively removable relative to the noble metal layer and the dielectric layer and capable of withstanding plasma etching. Alternately, the hard mask material may be consumable during the noble metal layer plasma etching. Plasma etching is performed on the noble metal layer in accordance with the patterned hard mask layer. The hard mask layer is removed such that a patterned shape formed in the noble metal layer remains in tact after the plasma etching and the hard mask removal.
Another method for forming a patterned shape from a noble metal, in accordance with the present invention includes forming a noble metal layer over a dielectric layer, and patterning a hard mask layer on the noble metal layer. The hard mask layer includes a mask material. The noble metal layer is plasma etched in accordance with the patterned hard mask layer wherein the mask material is consumed during the plasma etching such that at an end of the plasma etching a top surface of the noble metal layer remains covered by the mask material. The hard mask layer is removed selective to the noble metal layer and the dielectric layer such that a patterned shape formed in the noble metal layer and the dielectric layer remain intact after the plasma etching and the hard mask removal.
A method for forming a bottom electrode for a stacked capacitor structure of a semiconductor memory includes the steps of forming a dielectric layer on a substrate, the dielectric layer having conductive plugs formed therethrough, forming a noble metal layer on the dielectric layer in which the plug is electrically connected to the noble metal layer, patterning a hard mask layer on the noble metal layer, the hard mask layer including a mask material, plasma etching the noble metal layer in accordance with the patterned hard mask layer wherein the mask material is selectively removable relative to the noble metal layer during or after the plasma etching and removing the hard mask layer selective to the noble metal layer and the dielectric layer such that a patterned electrode is formed in the noble metal layer which remains intact after the plasma etching and the hard mask removal.
In other methods, the step of plasma etching may include performing a vertical side wall plasma etch at a target temperature of greater than about 200° C. The step of patterning the hard mask layer may include the step of providing a hard mask layer having at least two layers, and a top layer of the at least two layers may be selectively etchable relative to a lower layer of the at least two layers. One of the at least two layers may include one of boro-silicate glass, boro-phospho silicate glass and phospho silicate glass. One of the at least two layers may include silicon nitride. The hard mask layer may include at least one of boro-silicate glass, boro-phospho silicate glass, phospho silicate glass, TEOS oxide and silicon nitride. The step of forming a noble metal layer over a substrate may include the step of forming a barrier layer before forming the noble metal layer. This layer may be recessed into a plug via The step of forming a noble metal layer over a substrate may include the step of forming a barrier layer after forming the noble metal layer and etching through the barrier layer during the plasma etching. The barrier layers may include one of Ti, TiN, TiAlN, TaSiN, TaSi, TaAlN, IrO
x
, Ir, Al
2
O
3
, AlN, and SnO
x
.
In still other embodiments, the noble metal layer may include one of Pt, Iridium oxide, Ir, Ruthenium oxide, Pd, Os and Rh. The shape may include a bottom electrode for a stacked capacitor. The step of plasma etching may include etching the noble metal layer down to a first thickness in accordance with the patterned hard mask layer, raising a temperature of the noble metal layer and etching a remaining thickness of the noble in accordance with the patterned hard mask layer. The methods may further include the step of providing a dopant profile in the one of the at least two layers to provide a graduated etch rate therein. The methods may include the step consuming the mask material during the plasma etching such that at an end of the plasma etching a top surface of the noble metal layer remains covered by the mask material. The method may further include a second dielectric layer formed on the dielectric layer and further comprising the step of etching through the second dielectric layer during the plasma etching of the noble metal layer.
REFERENCES:
patent: 5591301 (1997-01-01), Grewal
patent: 5817553 (1998-10-01), Stengl et al.
patent: 5846884 (1998-12-01), Naeem et al.
patent: 5847423 (1998-12-01), Yamamichi
patent: 5930639 (1999-07-01), Schuele et al.
Athavale Satish D.
Kotecki David
Lian Jenny
Shen Hua
Braden Stanton C.
Goudreau George
Infineon Technologies North America Corp.
Mills Gregory
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