Easily testable high speed architecture for large RAMS

Details Easily testable high speed architecture for large RAMS Easily testable high speed architecture for large RAMS

1987-06-12

1989-05-23

Atkinson, Charles E.

Excavating

365201, G01R 3128

Patent

active

048336777

ABSTRACT:
The RAM is partitioned into modules, each of which appear as the leaf node of a binary interconnect network. This network carries the address/data/control bus which permits the nodes to communicate between themselves and with the outside world. The address, data and control signals are applied to the root node. The most significant address bit is decoded, generating either a left subtree or a right subtree select. The other signals would be buffered and propogated down the tree. The solution process occurs at each level within the bus until finally a single leaf node would be selected. Within the node, then, the internal timing and control unit would access the data requested, sending it up the tree or writing the value on the data bus, into the addressed location.

REFERENCES:
patent: 3351905 (1967-11-01), Kramer
patent: 4347498 (1982-08-01), Lee et al.
Horowitz, E. et al., "The Binary Tree as an Interconnection Network . . . ", IEEE Trans on Computers, vol. C-30, No. 4, Apr. 1981, pp. 247-253.
Bardell, Jr., P. et al., "Self-Test of Random Access Memories", 1985 International Test Conference, Paper 10.1, pp. 352-355.

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