Easily and quickly testable master-slave flipflop circuit

Details Easily and quickly testable master-slave flipflop circuit Easily and quickly testable master-slave flipflop circuit

1991-07-01

1992-04-14

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072721, 307279, 324158R, 371 223, H03K 3289, H04B 1700

Patent

active

051051001

ABSTRACT:
A master/slave flipflop comprises a master flipflop including a first inverter having an input for receiving an input signal, and a second inverter having an input connected to an output of the first inverter, and a first switch means connected between an output of the second inverter and the input of the first inventer. A slave flipflop of the master/slave flipflop includes a third inverter having an input for receiving an output signal of the master flipflop, and a fourth inverter having an input connected to an output of the third inverter, and a second switch means connected between an output of the fourth inverter and the input of the third inverter. A third switch is connected between the output of the second inverter and the input of the third inverter, and a fourth switch is connected between the output of the first inverter and the input of the third inverter. A controller controls the first to fourth switches so as to bring the first to third switches into off condition and also to bring the fourth switch into an on condition so that all the first to fourth inverters are cascaded.

REFERENCES:
patent: 4495629 (1985-01-01), Zasio et al.
patent: 4669061 (1987-05-01), Bhavsa
patent: 4782283 (1988-11-01), Zasio
patent: 4843254 (1989-06-01), Motegi et al.

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