Electricity: power supply or regulation systems – Self-regulating – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
1999-10-25
2001-02-27
Wong, Peter S. (Department: 2838)
Electricity: power supply or regulation systems
Self-regulating
Using a three or more terminal semiconductive device as the...
C323S313000
Reexamination Certificate
active
06194886
ABSTRACT:
FIELD OF INVENTION
This invention relates to current mirrors and more particularly to a compensation circuit for a cascode current mirror for cancelling Early voltage and base current errors.
BACKGROUND OF INVENTION
Many circuits rely on current mirrors for providing replicas of some input current. Current mirrors are designed to provide an output current which follows, or mirrors, the input current, or is a multiple thereof. However, inherent problems prevent the output current from identically matching the input current. Two problems in particular, base currents and base current modulation, contribute undesirable variations to the output current which result in an output current which does not follow the input current. Base currents, and hence base current errors, result from finite transistor beta. In contrast, finite Early voltage and changes in the mirror output voltage lead to base current modulation errors. While it has been possible to compensate for each of these respective errors individually, to date, it has not been possible to easily cancel both errors with a single, simple compensation circuit. This invention provides an auxiliary output node for sampling the cascode mirror output voltage without imposing a penalty in terms of simplicity, transistor count, compactness, or accuracy.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a compensation circuit for a cascode current mirror which cancels base current errors and base current modulation errors.
It is a further object of this invention to provide such a compensation circuit which simultaneously cancels both base current errors and base current modulation errors.
It is a further object of this invention to provide such a compensation circuit which cancels base current errors and base current modulation errors in a single circuit which is simple and easily implemented.
The invention results from the realization that a truly effective error compensated current mirror can be achieved with a compensation circuit which, in response to a change in the current mirror output voltage, applies the same change in voltage to a compensation stage which provides a change in current to the current mirror due to base current modulation effects inherent to the compensation stage to cancel base current modulation errors in the current mirror, the compensation circuit further using the base currents of the compensation circuit to cancel base current errors inherent to the current mirror so that output current of the current mirror mirrors the input current.
This invention features an Early voltage and beta compensated cascode current mirror. There is a cascode current mirror including an input stage, responsive to an input current, a current mirror circuit having a first stage responsive to the input stage and a second stage responsive to the first stage, and an output stage responsive to the second stage for providing an output voltage and current. There is a compensation circuit, responsive to the cascode current mirror, including a first compensation stage, a second compensation stage and a bootstrapping buffer stage, the first compensation stage, in response to a change in the output voltage, impresses a corresponding change in voltage on the second compensation stage, the second compensation stage thereby providing a change in current to the cascode current mirror for cancelling current errors induced by base current modulation in the output stage. The bootstrapping buffer, in response to the change in voltage, impresses an equal change in voltage on the first compensation stage to prevent errors from base current modulation effects in the first compensation stage. The first and second compensation stages further provide base current to the cascode current mirror for cancelling base current errors in the output current induced by the cascode current mirror.
In a preferred embodiment the input stage and first stage may form a first leg, the output stage and second stage may form a second leg and the first and second compensation stages may form a third leg, the first, second and third legs having normalized nominal currents of 1, Y, and Y·(1+Y), respectively, where Y is the current gain of the cascode current mirror. Each stage may include a transistor. The input transistor and first transistor may be diode connected. The first compensation transistor may provide a compensation current to the output transistor and the second compensation transistor may provide a compensation current to the second transistor to cancel base current errors. The bootstrapping transistor may be a PNP bipolar transistor and the first and second transistors may be NPN bipolar transistors. The bootstrapping transistor may be a NPN bipolar transistor, and the first and second transistor may be PNP bipolar transistor.
The invention also features a beta current and Early voltage compensation circuit for a current mirror with an output stage for providing an output voltage and current gain Y. There is a first compensation stage, responsive to a change in the output voltage; a second compensation stage, responsive to the first compensation stage, for providing a current to the output stage; and a bootstrapping buffer, responsive to the change in output voltage, the first compensation stage, in response to the change in the output voltage, impresses an equal change in voltage on the second compensation stage, the second compensation stage thereby providing a change in current to the current mirror for cancelling current errors induced by base current modulation in the output stage. The bootstrapping buffer, in response to the change in voltage, impresses a corresponding change in voltage on the first compensation stage to prevent errors from base current modulation effects in the first compensation stage, the first and second compensation stages further providing a base current to the cascode current mirror for cancelling base current errors in the output current by the cascode current mirror.
In a preferred embodiment the first and second compensation stages, or third leg, may have a normalized nominal current of Y·(1+Y) with respect to the first leg. Each stage may include a transistor. The bootstrapping transistor may be a PNP bipolar transistor, and the first and second compensation transistors are NPN bipolar transistors. The bootstrapping transistor may be an NPN bipolar transistor, and the first and second compensation transistors may be PNP bipolar transistors.
REFERENCES:
patent: 4398160 (1983-08-01), Neidorff
patent: 4814724 (1989-03-01), Tanigawa
patent: 5132556 (1992-07-01), Cheng
patent: 5164658 (1992-11-01), Kuwahara
patent: 5506543 (1996-04-01), Yung
patent: 5633612 (1997-05-01), Lee
patent: 5637993 (1997-06-01), Whitney et al.
patent: 5801523 (1998-09-01), Bynum
patent: 5867067 (1999-02-01), Moriarty, Jr.
patent: 6034518 (2000-03-01), Yuasa
Brokaw Adrian P.
D'Aquino Stefano I.
Tam Kimo Y. F.
Whitney David H.
Analog Devices Inc.
Iandiorio & Teska
Vu Bao Q.
Wong Peter S.
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