Early signaling of no-overflow for nonrestoring twos complement

Details Early signaling of no-overflow for nonrestoring twos complement Early signaling of no-overflow for nonrestoring twos complement

1995-06-16

1997-03-25

Malzahn, David H.

Boots, shoes, and leggings

3647365, G06F 752

Patent

active

056151136

ABSTRACT:
An early no-overflow signaling system and method is used in conjunction with performing nonrestoring division using two's complement 2n bit dividends N and two's complement n bit divisors D--when a no-overflow condition is signaled, a subsequent plurality of iterative partial remainder computations are performed to obtain the quotient Q and remainder R with no possibility of overflow. Dividends N are characterized by a 2-bit sign field N(s1s2) formed by a first sign bit N(s1) and a second sign bit N(s2), a high order n-1 dividend magnitude bits N(himag), and a low order n-1 dividend magnitude bits N(lomag), such that N(s1) and N(himag) form a 2's complement number N(hi), while divisors D are characterized by a leading sign bit D(s) and n-1 divisor magnitude bits D(mag). Early no-overflow signaling logic uses the input dividend N and divisor D, and a 2n-1 bit first partial remainder (which has a value of [N-2.sup.n-1 D]) obtained by computing an n-bit first partial remainder PR1 corresponding to the first n bits of the first partial remainder of value [N-2.sup.n-1 D] (including a leading sign bit PR1(s)), such that the first partial remainder of value [N-2.sup.n-1 D] corresponds to PR1 and N(lomag). No-overflow signaling (illustrated in FIGS. 2a/2b and 4) uses (i) the divisor sign and magnitude D(s) and D(mag), (ii) the two bit sign field of the dividend N(s1s2), (iii) and the first partial remainder of value [N-2.sup.n-1 D]. A no-overflow condition is signaled if (i) the divisor magnitude D(mag) is not equal to zero (FIG. 2a, 102, and FIG. 4, 151), and (ii) the dividend sign bits N(s1) and N(s2) are equal (FIG. 2a, 112, and FIG. 4 , 152), and (iii) the sign of the first partial remainder PR1(s) in not equal to the dividend sign bit N(s2) (FIG. 2b, 131, and FIG. 4, 153), and (iv) the divisor and dividend are not both negative (FIG. 2b, 141, and FIG. 4, 154, 156), or if they are, (v) the first partial remainder corresponding to PR1 and N(lomag) is not equal to zero (FIG. 2b, 141, 142, 143, and FIG. 2b, 155, 156).

REFERENCES:
patent: 4992968 (1991-02-01), Adiletta
patent: 5010511 (1991-04-01), Hartley et al.
patent: 5097435 (1992-03-01), Takahashi
patent: 5272660 (1993-12-01), Rossbach

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