Early instruction-length pre-decode of variable-length instructi

Details Early instruction-length pre-decode of variable-length instructi Early instruction-length pre-decode of variable-length instructi

1995-11-29

1998-09-15

Eng, David Y.

395388, G06F 930, G06F 938

Patent

active

058092722

ABSTRACT:
A superscalar processor can dispatch two instructions per clock cycle. The first instruction is decoded from instruction bytes in a large instruction buffer. A secondary instruction buffer is loaded with a copy of the first few bytes of the second instruction to be dispatched in a cycle. In the previous cycle this secondary instruction buffer is used to determine the length of the second instruction dispatched in that previous cycle. That second instruction's length is then used to extract the first bytes of the third instruction, and its length is also determined. The first bytes of the fourth instruction are then located. When both the first and the second instructions are dispatched, the secondary buffer is loaded with the bytes from the fourth instruction. If only the first instruction is dispatched, then the secondary buffer is loaded with the first bytes of the third instruction. Thus the secondary buffer is always loaded with the starting bytes of undispatched instructions. The starting bytes are found in the previous cycle. Once initialized, two instructions can be issued each cycle. Decoding of both the first and second instructions proceeds without delay since the starting bytes of the second instruction are found in the previous cycle. On the initial cycle after a reset or branch mis-predict, just the first instruction can be issued. The secondary buffer is initially loaded with a copy of the first instruction's starting bytes, allowing the two length decoders to be used to generate the lengths of the first and second instructions or the second and third instructions. Only two, and not three, length decoders are needed.

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