E.sup.2 PROM cell and architecture

Details E.sup.2 PROM cell and architecture E.sup.2 PROM cell and architecture

1985-10-15

1988-08-09

Fears, Terrell W.

Static information storage and retrieval

Format or disposition of elements

365189, G11C 1300, G11C 1142

Patent

active

047632992

ABSTRACT:
An architecture and memory cell of an E.sup.2 PROM array, and a process for forming a cell. The cell includes a channel oriented at 45.degree. relative to the bit lines of the array. A diffusion region in the architecture function as a terminal for four memory cells. The process for forming a cell provides for a floating gate having asperities on an erase segment but not on a programming segment.

REFERENCES:
patent: 4122544 (1978-10-01), McElroy
patent: 4267558 (1981-05-01), Guterman
patent: 4302766 (1981-11-01), Guterman et al.
patent: 4361847 (1982-11-01), Harari
Novram Reliability Report, Billy Kwong, Dr. John Caywood, Thurs., Feb. 14, 1985.
Electronics Week, p. 57, Fig. 8, Feb. 11, 1985.
Guterman et al., "An Electronically Alterable Nonvolatile Memory Cell Using a Floating-Gate Structure", IEEE J. Solid-State Circuits, vol. Sc-14, No. 2, pp. 498-508, Apr. 1979.

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