Dynamically variable length CPU pipeline for efficiently executi

Details Dynamically variable length CPU pipeline for efficiently executi Dynamically variable length CPU pipeline for efficiently executi

1997-12-19

2000-01-04

Follansbee, John A.

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate plural instruction...

712 43, G06F 930

Patent

active

060121386

ABSTRACT:
A processor for a data-processing system is provided with a dynamically reconfigurable multistage pipeline which permits the execution of more than one instruction set by the processor utilizing the same instruction decoding circuitry and instruction execution control logic circuitry. In one embodiment, the pipeline includes an instruction fetch stage, an instruction conversion stage, an instruction decode stage, and a multiplexer which is used to switch the instruction conversion stage into and out of the pipeline between the instruction fetch stage and the instruction decode stage, even while instructions continue to be executed by the pipeline. The multiplexer operates under control of the instruction decode stage and may be set in response to decoded instructions. The instruction fetch stage is coupled to a bus to retrieve an instruction at a location specified by a program counter. The instruction conversion stage is coupled to the instruction fetch stage to receive the instruction and is configured to convert the instruction from a non-native instruction set to a corresponding instruction in a native instruction set. The multiplexer is coupled to the instruction fetch stage and to the instruction conversion stage. The multiplexer is configured to forward the converted instruction from the instruction conversion stage if a mode bit is set, and is further configured to forward the instruction from the instruction fetch stage if the mode bit is reset. The instruction decode stage is coupled to the multiplexer to receive a native instruction and is configured to identify instruction operands for the native instruction.

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