Dynamically scalable low voltage clock generation system

Details Dynamically scalable low voltage clock generation system Dynamically scalable low voltage clock generation system

2001-10-11

2003-02-04

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

Reexamination Certificate

active

06515530

ABSTRACT:

TECHNICAL FIELD
The present invention relates in general to circuits for generating and controlling computer clocks.
BACKGROUND INFORMATION
Phase lock loops (PLL's) have been widely used in high-speed communication systems because PLL's efficiently perform clock recovery or clock generation at a relatively low cost. Dynamic voltage and frequency scaling is a critical capability in reducing power consumption of power sensitive devices. Scaling, in this sense, means the ability to select a high performance with nominal power supply voltages and high frequency clock operation, or a lower performance by reducing the power supply voltage and corresponding the clock frequency. Reducing the system power is usually done when performance is not needed or when running from a limited energy source such as a battery. To allow low power operation, the PLL and other circuits support very aggressive power/energy management techniques. For the PLL, this means low power operation while supporting key required features such as dynamic frequency scaling, dynamic voltage scaling, clock freezing, and alternate low frequency clocking. Dynamic scaling implies that the PLL is able to support changes in the system clock frequency and logic supply voltage without requiring the system to stop operation or wait for the PLL clock to relock on the new clock frequency.
Using a PLL has advantages in a battery powered system because a PLL is able to receive a lower frequency reference frequency from a stable oscillator to generate higher system clock frequencies. A PLL also allows changing the system clock frequency without changing the reference frequency. The prior art has described ways of selecting operating points of voltage and frequency statically, for example stopping execution while allowing the PLL to relock to a new frequency. This slows system operations and complicates system design. A delay-locked loop (DLL) may also be used to generate a high fixed frequency.
There is, therefore, a need for a clock generation system based on a PLL that allows the benefits of a PLL to be used during frequency and voltage scaling without requiring the system to halt operation. There is also a need for a clock generation system based on a PLL that allows optimization of power dissipation by allowing the PLL to operate at the highest frequency possible at a set system logic power supply voltage.
SUMMARY OF THE INVENTION
A phase locked loop (PLL) has a programmable frequency divider (PRFD) that divides the output of the PLL to generate a feedback clock (FBCLK) which is compared to a reference clock (RCLK) in a phase/frequency comparator. The PLL output is divided in a second PRFD to generate a divided PLL output clock. The PLL is powered from a scalable logic power supply voltage of a system that employs dynamic frequency and voltage scaling to manage energy consumption of the system. The PLL power supply and reference voltages are generated by voltage regulating the scalable logic power supply voltage. The PLL supply voltage is less than the lowest voltage level of the scalable logic power supply voltage used in the system. The PLL is designed to operate at the highest frequency of the system when the system uses the highest level of the scalable logic power supply voltage. A fixed frequency clock and the PLL output clock are multiplexed (MUX) in a glitch-less circuit under system control to supply the system clock. The scalable logic power supply voltage may be varied without affecting operation of the PLL. If the scalable logic power supply voltage level is to be lowered below a level that supports the existing system clock frequency, then the system clock frequency is first lowered by programming the frequency divider that divides the PLL output. The divisor of the second PRFD may be dynamically changed without switching to the fixed frequency clock. A valid signal from the second PRFD is generated indicating when its divisor may be changed without causing glitches in its output. If the frequency of the PLL is to be altered, then the MUX selects the fixed frequency clock as the system clock, then programs the PLL and waits for it to stabilize, then the PLL output clock is again switched back as the system clock. The system clock signal is stopped, if necessary, in a known logic state by an appropriate signal sent to circuits in the MUX selecting the system clock signal. The logic employed in stopping and starting the system clock signal use a clock separate from the system clock signal. The scalable logic power supply voltage and the system clock frequency are dynamically scaled to manage system energy consumption and to optimize performance at a given energy consumption level. In one embodiment the scalable logic power supply voltage may be supplied by a battery whose voltage may change due to battery discharge. The battery voltage is monitored and the system clock frequency is dynamically scaled when necessary without affecting the PLL.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.


REFERENCES:
patent: 6031429 (2000-02-01), Shen
patent: 6066990 (2000-05-01), Genest
patent: 6298448 (2001-10-01), Shaffer et al.

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