Dynamically reconfigurable signal processing circuit,...

Details Dynamically reconfigurable signal processing circuit,... Dynamically reconfigurable signal processing circuit,...

2006-08-08

2006-08-08

Desire, Gregory (Department: 2624)

Image analysis

Pattern recognition

C348S222100, C348S571000, C382S145000, C382S247000

Reexamination Certificate

active

07088860

ABSTRACT:
A plurality of signal processing functions are achieved with the same arithmetic processing circuit by controlling wiring arrangements or signal modulation in accordance with a predetermined arrangement control signal that is output based on circuit arrangement information read from a circuit arrangement information storage unit. Hierarchical parallel processing is realized with small-scale circuit configuration. Further, detection of a predetermined feature and integration of the detection results can be efficiently performed.

REFERENCES:
patent: 4786818 (1988-11-01), Mead et al.
patent: 5220559 (1993-06-01), Tsuzuki et al.
patent: 5459424 (1995-10-01), Hattori
patent: 5519811 (1996-05-01), Yoneda et al.
patent: 5805605 (1998-09-01), Lee et al.
patent: 5959871 (1999-09-01), Pierzchala et al.
patent: 5987170 (1999-11-01), Yamamoto et al.
patent: 5999055 (1999-12-01), Kimura
patent: 6321174 (2001-11-01), Chen et al.
patent: 6597394 (2003-07-01), Duncan et al.
patent: 6606119 (2003-08-01), Shibata et al.
patent: 6741198 (2004-05-01), McIlrath
patent: 6928535 (2005-08-01), Yamashita et al.
patent: 6947088 (2005-09-01), Kochi
patent: 2002/0008309 (2002-01-01), Akiyama
patent: 2002/0038294 (2002-03-01), Matsugu
patent: 2002/0101528 (2002-08-01), Lee et al.
patent: 2002/0181799 (2002-12-01), Matsugu et al.
patent: 2003/0154357 (2003-08-01), Master et al.
patent: 2005/0021578 (2005-01-01), Chen et al.
patent: 0 926 885 (1999-06-01), None
patent: 1 164 537 (2001-12-01), None
patent: 05-037317 (1993-02-01), None
patent: 06-061808 (1994-03-01), None
patent: 06-176158 (1994-06-01), None
patent: 07-235839 (1995-09-01), None
patent: 09-153021 (1997-06-01), None
patent: 2679730 (1997-08-01), None
patent: 2741793 (1998-01-01), None
patent: 10-327054 (1998-12-01), None
patent: 11-015945 (1999-01-01), None
patent: 11-068477 (1999-03-01), None
patent: 11-168185 (1999-06-01), None
patent: 11-196332 (1999-07-01), None
patent: 11-266002 (1999-09-01), None
patent: 2000-013694 (2000-01-01), None
patent: 2000-181487 (2000-06-01), None
patent: 2000-331113 (2000-11-01), None
Daugman, “Complete Discrete 2-D Gabor Transforms by Neural Networks for Image Analysis and Compression,” 36 (7) IEEE Trans. on Acoustics, Speech, and Signal Processing, 1169-1179 (1988).
Daugman, “Uncertainty Relation for Resolution in Space, Spatial Frequency, and Orientation Optimized by Two-Dimensional Visual Cortical Filters,” 2 (7) Journal of Optical Society of America A, 1160-1169 (1985).
Funatsu et al., “Artificial Retina LSI and its Application Systems,” 53 (2) Journal of Institute of Image Information and Television Engineers, 178-183 (1999).
Kung, “Digital Neural Networks,” PTR Prentice Hall, 340-361 (1993).
Lazzaro et al., “Silicon Auditory Processors as Computer Peripherals,”, Advances in Neural Information Processing Systems 5, San Mateo, CA, Morgan Kaufmann Publishers, 820-827 (1993).
LeCun et al., “Convolutional Networks for Images, Speech, and Time Series,” The Handbook of Brain Theory and Neural Networks (M. Arbib, Ed.), MIT Press, 255-258 (1995).
Shi, “Gabor-Type Filtering in Space and Time with Cellular Neural Networks,” 45 (2) IEEE Transactions on Circuits and Systems-1: Fundamental Theory and Applications, 121-132 (1998).
Shi, “2D Focal Plane Steerable and Scalable Cortical Filters,” IEEE Proc. of Seventh International Conference on Microelectronics for Neural, Fuzzy, and Bio-Inspired Systems, 232-239 (1999).
Shi, “Subthreshold Current Mode Design of Gabor-type CNN Image Filters”, Proc. European Conference on Circuit Theory and Design, 1163-1169 (1999).
IEE Transactions on Neural Networks, vol. 10, No. 3, May, 1999, p. 540.
Shinji Tomita, “Parallel Computer Configuration Theory”, Shokodo, 1986, pp. 190-192.
C. Mead et al., “Analog VLSI and Neural Systems”, Addison Wesley Pub., 1989, pp. 257-278 (Chapter 15—Silicon Retina).

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