Dynamically reconfigurable array logic

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307465, G06F 738, H03K 1920

Patent

active

047916036

ABSTRACT:
A dynamically reconfigurable array logic (DRAL) is capable of in-system logical reconfiguration in real time and comprises a RAM programmable logic array of bits, each bit comprising a fuse connection between logic elements. I/O means are coupled to the RAM programmable logic array for logical selection of registered output. A first register is coupled for receiving data and high-level commands. A sequencer includes a pair of up/down counters and functions to generate addresses. A timing device controls DMA transfers and issues READ and WRITE strobes. A second register monitors outputs and functions as a comparator, in a first mode, and functions to load outputs during specified time intervals in a second mode.

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