Dynamically controlled voltage regulator for a memory

Details Dynamically controlled voltage regulator for a memory Dynamically controlled voltage regulator for a memory

2011-04-12

2011-04-12

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Powering

C365S154000, C365S229000

Reexamination Certificate

active

07924650

ABSTRACT:
A memory device that includes multiple blocks of static random access memory (SRAM), which each have a standby mode and an active operating mode, is described. During the active operating mode, a selection circuit couples a higher voltage from a first power-signal line and a power-supply circuit to a given block of SRAM, and during the standby mode the selection circuit couples a lower voltage from a second power-signal line to the given block of SRAM. Note that a regulator circuit regulates the lower voltage on the second power-signal line by selectively opening or closing a first switch between the first power-signal line and the second power-signal line. Furthermore, a recycling circuit selectively opens a second switch between the first switch and the first power-signal line when the block of SRAM transitions from the active operating mode to the standby mode, thereby transferring charge from the block of SRAM to other blocks of SRAM.

REFERENCES:
patent: 5901103 (1999-05-01), Harris et al.
patent: 7360006 (2008-04-01), Ho et al.
Cho, Hoyoel et al., U.S. Appl. No. 12/340,529, filed Dec. 19, 2008, entitled “Method and Apparatuses for Improving Reduced Power Operations in Embedded Memory”.

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