Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2001-05-23
2003-02-25
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S200000, C365S230020
Reexamination Certificate
active
06525987
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to memory systems, and more particularly, to a memory system, which detects errors and reconfigures itself to avoid bad memory cells.
BACKGROUND OF THE INVENTION
As the cost of computational hardware has decreased, computers with ever-larger memory systems have proliferated. Systems with hundreds of Mbytes are common, and systems with a few Gbytes of memory are commercially available. As the size of the memory increases, problems arising from bad memory cells become more common.
Memory failures may be divided into two categories, those resulting from bad memory cells that are detected at the time of manufacture and those that arise from cells that fail during the operation of the memory. At present, problems arising from defective memory cells that are detected during the manufacturing process are cured by replacing the bad cells. The typical memory array is divided into blocks. Each memory chip has a predetermined number of spare blocks fabricated thereon. If a block in the memory is found to have a defective memory cell, the block in question is disconnected from the appropriate bus and one of the spares is connected to the bus in its place. However, once the part is packaged, there are no means available for replacing a block with a spare, since the replacement process requires hard wiring of the spares to the bus.
The cost of testing the memory chips is a significant factor in the cost of the chips. The rate at which memory cells can be tested is limited by the internal organization of the memory blocks and the speed of the buses that connect the memory blocks to the test equipment. The various buses are limited to speeds of a few hundred MHz. Data is typically written and read as blocks having 64 bits or less. Since a write operation followed by a read operation requires several clock cycles, the rate at which memory can be tested is limited to 100 million tests per second. Extensive testing requires each memory cell to be accessed a large number of times under different conditions such as temperature and clock speed. Hence, a 1 Gbyte memory chip would require minutes, if not hours, to thoroughly test. The cost of such testing would be prohibitive; hence, prior art memory chip designs will not permit extensive testing at the 1 Gbyte level and beyond.
In principle, all of these types of memories would benefit by having some form of reconfiguration system built directly into the memory. Such a system is described in U.S. Pat. No. 6,236,602 which is hereby incorporated by reference. In this type of system the memory is constructed with blocks of memory cells that include spare cells. The memory cells have physical addresses that relate to the location of the memory cells in the physical memory blocks that make up the memory. The memory stores and retrieves data with respect to logical addresses that are utilized by processors connected to the memory to specify data stored, or to be stored, in the memory. The correspondence between the logical and physical address is held in a mapping processor that is under the control of a controller in the memory. When bad memory cells are detected by the controller, the mapping is altered by mapping the corresponding bad cell logical address to the spare memory cells contained in the memory.
While the memory scheme taught in the above-identified patent substantially improves many aspects of memory performance and memory yields, the mapping processors increase the cost of the memory chips. In the scheme described in the above-identified patent, the memory is constructed from blocks of memory cells organized as a plurality of rows and columns. The memory processors are implemented using content-addressable memories (CAMs) that store the logical addresses corresponding to each row in the memory. These CAMs can be a significant fraction of the memory area, and hence, it would be advantageous to provide a memory mapping scheme that requires less chip area.
Broadly, it is the object of the present invention to provide an improved reconfigurable memory system.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the preferred embodiments of the invention and the accompanying drawings.
SUMMARY OF THE INVENTION
The present invention is a memory for storing and retrieving data values, each data value being associated with a row address. The memory includes an array of memory storage cells organized as R rows and C columns, each storage cell being connected to one of C bit lines and one of R row lines. Each memory storage cell stores a data value and includes circuitry for coupling that data value to the bit line to which that memory cell is connected in response to a row control signal on the row line to which that memory cell is connected. The memory includes a row select circuit for generating the row control signal on one of the row lines in response to one of the row addresses being coupled to the row select circuit. The row select circuit includes a memory for storing a mapping of the row addresses to the row lines, the mapping determining which of the row lines is selected for each possible value of the row address. The R row lines are divided into N
r
normal row lines and N
rs
spare row lines. The row select circuit includes first and second decoding circuits. The first decoding circuit generates one of the row select signals on one of the N
r
normal row lines in response to the row address being coupled thereto. In addition, the first decoding circuit includes an inhibit circuit for preventing that row select signal from being applied to that normal row line. The second decoding circuit stores N
rs
entries, each entry having a space for storing a first value specifying one of the row addresses and a second value specifying one of the N
rs
spare row lines. The second decoding circuit determines if one of the entries includes a first value that matches the row address and causes the inhibit circuit in the first decoding circuit to prevent the application of the row select signal. The second decoding circuit then generates one of the row select signals on the spare row line specified by the second value in that entry.
In one embodiment of the invention, the memory also includes a column select circuit for selecting a data value on one of the bit lines and applying that data value to an output line in response to a column address being coupled to the column select circuit. In this embodiment, the C bit lines are divided into N
c
normal bit lines and N
cs
spare bit lines, N
c
and N
cs
being greater than 0. The column select circuit includes a column multiplexer, and third and fourth decoding circuits. The column multiplexer connects one of the bit lines to the output line in response to a column select signal on one of the C column select lines, the column select line receiving that signal determining which of the bit lines is connected to the output line. N
c
of the column select lines correspond to the normal bit lines and N
cs
of the column select lines correspond to the spare bit lines. The third decoding circuit generates one of the column select signals on one of the N
c
normal column select lines in response to the column address being coupled thereto, and includes an inhibit circuit for preventing that column select signal from being applied to that normal column select line. The fourth decoding circuit stores N
cs
entries, each entry having space for storing a first value specifying one of the column addresses and a second value specifying one of the N
cs
spare bit lines. The fourth decoding circuit determines if one of the entries includes a first value that matches the column address and causes the inhibit circuit in the third decoding circuit to prevent the application of the column select signal. The fourth decoding circuit also generates one of the column select signals on the spare column select line corresponding to the spare bit line specified by the second value in that entr
Le Thong
Nelms David
Tachyon Semiconductor Corporation
Ward Calvin B.
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