Dynamically configurable variable frequency and duty cycle clock

Details Dynamically configurable variable frequency and duty cycle clock Dynamically configurable variable frequency and duty cycle clock

1998-06-02

2000-03-21

Wambach, Margaret R.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

327115, 327116, 327298, 377 54, H03K 104

Patent

active

060407255

ABSTRACT:
A variable clock generator includes a clock multiplier that generates from a reference clock at least two clock signals which are out of phase with each other and a clock divider which receives a plurality of divider patterns and which receives at least two clock signals from the clock multiplier. The clock divider generates an output clock based on the divider patterns and the clock signals. In a particular embodiment, the clock divider includes a plurality of loadable linear feedback shift registers each having an output. An EXCLUSIVE OR gate that is responsive to the outputs of the linear feedback shift registers then EXCLUSIVE ORs the outputs of the linear feedback shift registers to produce the output clock. Preferably, the size of the linear feedback shift registers corresponds to the size of the divider patterns.

REFERENCES:
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patent: 5144571 (1992-09-01), Thong
patent: 5337339 (1994-08-01), Hillstrom
patent: 5345109 (1994-09-01), Mehta
patent: 5371772 (1994-12-01), Al-Khairi
patent: 5477181 (1995-12-01), Li et al.
patent: 5687202 (1997-11-01), Eitrheim
patent: 5719510 (1998-02-01), Weidner
Programmable Square-Wave Clock Divider, IBM Technical Disclosure Bulletin, vol. 30, No. 12, pp. 11-13 (May 1988).
Integer Divisible Frequency Divider with Symmetric Outputs, IBM Technical Disclosure Bulletin, vol. 39, No. 05, pp. 187-188 (May 1996).

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