Patent
1997-02-27
1998-06-16
Gossage, Glenn
395556, 395559, 39549701, G06F 1300, G06F 108
Patent
active
057685606
ABSTRACT:
A memory system includes a memory and a controller coupled to the memory and a system bus. The controller is configured to receive a bus clock and control signals over the system bus and to provide memory control signals with a predetermined timing resolution to the memory. The controller includes a bus clock frequency multiplication circuit for generating an internal clock signal which is used to generate the memory control signals, and a programmable timing register for storing timing intervals of the memory control signals. The bus frequency multiplication circuit generates the internal clock signal by multiplying the frequency of the bus clock by a bus frequency multiplication factor which is selectively chosen to set the predetermined timing resolution for the memory control signals to a nearly constant value independent of the frequency of the bus clock. The bus frequency multiplication circuit may comprise a phase locked loop.
REFERENCES:
patent: 4523274 (1985-06-01), Fukunaga et al.
patent: 5077686 (1991-12-01), Rubinstein
patent: 5097437 (1992-03-01), Larson
patent: 5208838 (1993-05-01), Wendell et al.
patent: 5256994 (1993-10-01), Langendorf
Lieberman Donald A.
Nemec John J.
Cypress Semiconductor Corp.
Gossage Glenn
LandOfFree
Dynamically configurable memory system having a programmable con does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Dynamically configurable memory system having a programmable con, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dynamically configurable memory system having a programmable con will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1738164