Dynamically alterable interrupt priority circuit

Details Dynamically alterable interrupt priority circuit Dynamically alterable interrupt priority circuit

1983-11-03

1992-01-21

Lee, Thomas C.

Boots, shoes, and leggings

3642426, 3642418, 3642612, 364DIG1, G06I 1326

Patent

active

050832611

ABSTRACT:
An interrupt priority circuit is used with a data processor which is responsive to interrupt signals from each of a plurality of resources of predetermined priority. A priority encoder receives all of the interrupt signals, and provides an interrupt vector corresponding to the interrupt signal received from the resource having the highest predetermined priority. However, the interrupt priority of a selected resource may be dynamically altered to the highest priority by storing a corresponding priority vector into a priority register. A first multiplexor controlled by the priority vector provides an enable signal whenever an interrupt signal is received from the selected resource. A second multiplexor controlled by the enable signal provides the priority vector if the enable signal is present or the interrupt vector otherwise. A gate controlled by the data processor may be provided to selectively couple the vector provided by the second multiplexor onto the address bus.

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Z8 Family of Microcomputers Z8601, Z8602, Z8603, Product Specification, Jun. 1982, pp. 431-441.
Intel Microcontroller Handbook, 1983, Chapter 6, MCS-51 Architecture, pp. 6-24-6-25.

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